1. Field of the Invention
This invention generally relates to carriers for electronic components and more specifically to carriers for facilitating the handling of electronic components in transistor outline packages.
2. Description of Related Art
Semiconductor devices have matured from simple circuit elements into complex components provided in a variety of integrated circuit packages, such as transistor outline (TO), flatpack and pin grid array (PGA) packages. This maturation has been accompanied by an increase in the complexity of handling these components during assembly and testing operations. For example, components in TO packages have a large number of terminals and can be quite expensive. Typically a number of TO and other components occupy different positions on a single circuit board.
Components in TO and other packages are more susceptible to damage from a number of external influences, such as mechanical shock and discharges of accumulated electrostatic charge, than were prior components. The consequence of potential damage and other factors has led to changes in transportation, assembly and testing procedures that utilize such components. Indeed, procedures for handling the components now contribute significantly to the success of electronic assembly production. For example, when electronic components comprised simple transistors, resistors and capacitors, all the components would be assembled on a board without prior testing. If a component failed, debugging procedures were used to isolate defective components; then they were replaced.
It no longer is economically feasible to replace TO and other integrated circuits and similar components it they are mounted on a board. It is easier to discard the entire board with a number of valuable working components than it is to replace a single failed integrated circuit. Thus, present procedures involve component testing prior to assembly to minimize the risk of mounting a defective component. Although this adds costs to the assembly process, overall the added costs are less than those encountered when a board is assembled with a defective component and discarded.
The need to protect and test integrated circuits during assembly operations led to the development of chip carriers. Chip carriers are special enclosures or packages that house and protect an integrated circuit or the like during processing, production, testing and assembly operations. More specifically, a chip carrier orients an integrated circuit during the production process, assures proper placement and alignment of terminals for testing and for insertion into a printed circuit board. It eliminates stresses from the terminals and seals found in such an integrated circuit. Chip carriers now must protect a component from mechanical and electrical damage, provide access to all the terminals to facilitate component testing and minimize damage due to discharges of accumulated electrostatic charges if the chip carrier is to be acceptable.
As the number of integrated circuit designs and packages have proliferated, so have the number of chip carrier configurations Indeed there are different chip carrier structures for different integrated circuit packages, including chip carriers exclusively for components in TO packages. These carriers have a profile that is similar to the profile shown in FIG. 1 of the attached drawings. In such a carrier, a central planar portion extends along a travel axis. The travel axis typically lies along a direction of travel. Integral elevated side rails parallel to the axis provide a means for engagement by tracks, conveyors or tooling in a conventional electronic assembly lines thereby to manipulate the carrier. The carrier contains notches and grooves to further facilitate transportation and manipulation. These carriers are molded with a TO package support structure extending along an axis transverse to the plane of the carrier and the travel axis. This support structure generally comprises of fins that radiate from a core member to define segments that guide terminals through apertures in a supporting web. The diameters of the apertures correspond to the diameters of terminals from the TO package. The radial fins extend below the planar base for separating the terminals physically and are coextensive with the length of the terminals.
These prior carriers have been constructed during a single injection molding process using either an insulating material or an insulating material filled with a conductive material. In the former case the carrier isolates the electrical leads for component electrical testing prior to assembly. However, electrostatic charges can accumulate on such carriers and eventually may discharge and damage the components in the TO package. When the TO carrier is constructed with a material containing a conductive filler, the percentage of the filler determines the electrical conductivity characteristics of the carrier. If sufficient filler is utilized, the carrier is conductive and minimizes any accumulation of electrostatic charge. However, it is difficult to test the component because the terminals no longer are isolated electrically. Moreover, filled plastic tends to be rigid, and not so resilient as unfilled plastic. Any sliding motion between the terminals and the apertures in the supporting structure can damage the terminals particularly by eroding any plating materials on the terminals.
Theoretically a certain precise filler percentage might establish a conductivity level that was sufficient to avoid electrostatic charge accumulation, but still provide an impedance between the various terminals that was much greater than the input impedances between those terminals. In practice it is difficult, if not impossible, to control the fill fractions in injection molding materials with such precision. Thus, this approach has not gained commercial acceptance.